Product Summary

The MC68MH360ZP25LR2 is an Quad Integrated Communication Controller (QUICC). It is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. The MC68MH360ZP25LR2 particularly excels in communications activities. The QUICC (pronounced quick) can be described as a next-generation MC68MH360ZP25LR2 with higher performance in all areas of device operation, increased flexibility, major extensions in capability, and higher integration. The term quad comes from the fact that there are four serial communications controllers (SCCs) on the MC68MH360ZP25LR2; however, there are actually seven serial channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).

Parametrics

MC68MH360ZP25LR2 absolute maximum ratings: (1)Supply Voltage, VCC: –0.3 to +6.5 V; (2)Input Voltage, Vin: –0.3 to +6.5 V; (3)Operating Temperature Range, TA: 0 to 70 or –40 to +85℃; (4)Maximum operating Junction Temperature, TJ: 115℃; (5)Minimum operation Ambient Temperature, TA: 0℃; (6)Storage Temperature Range Tstg: –55 to +150℃.

Features

MC68MH360ZP25LR2 features: (1)CPU32+ Processor (4.5 MIPS at 25 MHz): 32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32); Background Debug Mode; Byte-Misaligned Addressing; (2)Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits); (3)Up to 32 Address Lines (At Least 28 Always Available); (4)Complete Static Design (0–25-MHz Operation); (5)Slave Mode To Disable CPU32+ (Allows Use with External Processors); (6)Multiple QUICCs Can Share One System Bus (One Master); (7)MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion ; (8)Chip and Intelligent Peripheral (22 MIPS at 25 MHz); (9)Also Supports External MC68030-Type Bus Masters ; (10)All QUICC Features Usable in Slave Mode; (11)Memory Controller (Eight Banks); (12)Contains Complete Dynamic Random-Access Memory (DRAM) Controller; (13)Each Bank Can Be a Chip Select or Support a DRAM Bank; (14)Up to 15 Wait States.

Diagrams

MC68MH360ZP25LR2 block diagram

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